The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Mar. 18, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Andrew Thomas Novotny, Santa Clara, CA (US);

Roger D. Flateau, Jr., San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 13/20 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0772 (2013.01); G06F 11/0745 (2013.01); G06F 11/0751 (2013.01); G06F 13/20 (2013.01);
Abstract

Embodiments herein describe error interceptors disposed along a bus that communicatively couples first and second circuits for redirecting in-band errors. That is, the error interceptors can block (or mask) in-band errors so they are not forwarded along the bus. Further, the error interceptors can redirect those errors such that they are converted into out-of-band errors. Moreover, the user can select which error interceptors to activate (e.g., block and redirect the errors) and which to deactivate (e.g., permit the in-band errors to pass). In this manner, the user can control which circuits receive in-band errors and which do not based on whether those circuits can handle the in-band errors.


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