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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11422876 B1

PDFFull Text
Date of Patent:
Aug. 23, 2022

Filed:

Aug. 02, 2019

Systems and methods for monitoring and responding to bus bit error ratio events

Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Jeffrey Matthew Shuey, Bothell, WA (US);

Neeraj Ladkani, Bothell, WA (US);

Tao Liu, Bellevue, WA (US);

Subhasish Chakraborty, Seattle, WA (US);

Assignee:

MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US);

Attorneys:

Ray Quinney & Nebeker

Tiffany Healy

Primary Examiner:

Charles Ehne

Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 11/10 (2006.01); G06F 11/16 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 11/076 (2013.01); G06F 9/4856 (2013.01); G06F 9/505 (2013.01); G06F 9/5088 (2013.01); G06F 11/0793 (2013.01); G06F 11/1048 (2013.01); G06F 11/1625 (2013.01); G06F 11/3027 (2013.01);
Abstract

A computer system includes a bus interface having error correction capability. The bus interface includes an error register that is configured to provide error information related to correctable errors. System software within the computer system is configured to obtain the error information from the error register and calculate a bit error metric based on the error information. A baseboard management controller within the computer system is configured to take an action in response to obtaining the bit error metric from the system software and determining that a condition related to the bit error metric has been satisfied.

Find Patent Forward Citations

Shuey, Jeffrey. (2022). Systems and methods for monitoring and responding to bus bit error ratio events (U.S. Patent No. 11422876). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11422876

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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