The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Dec. 05, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Deric Waters, Dallas, TX (US);

Bill Waters, Portland, OR (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 13/38 (2006.01); G06F 1/3296 (2019.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 1/266 (2013.01); G06F 1/3296 (2013.01); G06F 13/385 (2013.01); G06F 13/4282 (2013.01); Y02D 10/00 (2018.01);
Abstract

An apparatus, comprising a system management bus configured to communicate with a USB PDC, and a processor coupled to the system management bus and configured to send a power delivery configuration to the PDC, wherein the power delivery configuration comprises voltage and current settings, and receive a power delivery status from the PDC. Also disclosed is an apparatus comprising a power bus interface configured to communicate with a USB port partner, a system management bus interface configured to communicate with a host, and a processor coupled to the power bus interface and the system management bus interface, wherein the processor is configured to receive, via the system management bus interface, a power delivery configuration from the host, generate a power capability message based on the power delivery configuration, and send, via the power bus interface, the power capability message to the USB port partner.


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