The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2022
Filed:
Feb. 02, 2021
Texas Instruments Incorporated, Dallas, TX (US);
Todd Christopher Hiers, Houston, TX (US);
Chunhua Hu, Plano, TX (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.