The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

May. 21, 2021
Applicants:

Infineon Technologies Ag, Neubiberg, DE;

Politecnico Di Milano, Milan, IT;

Inventors:

Dmytro Cherniak, Villach, AT;

Salvatore Levantino, Mailand, IT;

Alessio Santiccioli, Castiglion Fiorentino, IT;

Assignees:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

POLITECNICO DI MILANO, Milan, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/087 (2006.01); H03L 7/099 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03L 7/087 (2013.01); H03L 7/099 (2013.01); H04L 7/0331 (2013.01);
Abstract

In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.


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