The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2022
Filed:
Apr. 30, 2020
Battelle Memorial Institute, Richland, WA (US);
Jesse T. Holzer, Kennewick, WA (US);
Yonghong Chen, Zionsville, IN (US);
Feng Pan, Sugar Land, TX (US);
Edward Rothberg, Portland, OR (US);
BATTELLE MEMORIAL INSTITUTE, Richland, WA (US);
Abstract
Fast simultaneous feasibility testing (SFT) for management of an electrical power grid is achieved through various innovations. The computation problem relates to evaluation of candidate solutions for external power flows into a power grid, with respect to predetermined constraints and contingencies. Storage and computations are reduced by formulating the problem in terms of transactional nodes (e.g. third party connections for generators and loads) instead of the larger number of bus nodes. Further advantages are achieved by precomputing matrices that can be reused across multiple SFT invocations, organizing matrices and operations to reduce storage and computation, and eliminating branches that have no contingency violations. The fast SFT further enables new applications for integrating SFT with a Security-Constrained Unit Commitment (SCUC) optimizer for efficient single pass solutions; operating SFT as a service to multiple SCUC solvers; or integration with Security-Constrained Economic Dispatch (SCED) optimization.