The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

Feb. 26, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Hiroyuki Hara, Fujisawa Kanagawa, JP;

Yoshinori Suzuki, Chigasaki Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0069 (2013.01); H01L 27/2409 (2013.01); H01L 45/06 (2013.01); H01L 45/126 (2013.01); H01L 45/144 (2013.01); G11C 2213/72 (2013.01);
Abstract

A semiconductor storage device includes lower and upper bit lines, word lines between the bit lines, and memory cells between the bit lines and the word lines. The memory cells are divided into logical slices and a memory cell from each logical slice is selected when carrying out a read or write operation. A first logical slice includes memory cells, each of which is between one of two bit lines and one of three word lines that are adjacent to each other. The two bit lines include one lower bit line and one upper bit line. A second logical slice includes memory cells, each of which is between one of three bit lines and one of three word lines that are not adjacent to each other. The three bit lines include one lower bit line and two upper bit lines.


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