The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

Nov. 27, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Bong-Soo Kim, Sejong-si, KR;

Juhyeon Kim, Cheonan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/5283 (2013.01);
Abstract

Provided is a semiconductor package including a redistribution substrate, a connection substrate on the redistribution substrate, the connection substrate having an opening that penetrates the connection substrate, a semiconductor chip in the opening of the connection substrate, and a molding layer that covers the semiconductor chip and the connection substrate, and fills a space between the semiconductor chip and the connection substrate, the connection substrate includes a base layer, a plurality of vias that vertically penetrate the base layer, a plurality of first patterns on a top surface of the base layer and connected to the plurality of vias, and a plurality of second patterns on a bottom surface of the base layer and connected to the plurality of vias, an extension of the molding layer extends into a plurality of holes that are spaced apart from the plurality of vias and are formed to vertically penetrate the base layer.


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