The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

Aug. 31, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Mario Sako, Yokohama Kanagawa, JP;

Hiromitsu Komai, Kamakura Kanagawa, JP;

Masahiro Yoshihara, Yokohama Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); H01L 23/522 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 27/11529 (2017.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); H01L 23/5223 (2013.01); G11C 2216/20 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract

A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.


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