The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

Oct. 22, 2020
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Cheng-Chen Huang, Hsinchu, TW;

Yun-Ru Wu, Hsinchu, TW;

Hsin-Chang Lin, Zhubei, TW;

Shu-Yi Kao, Zhubei, TW;

Chih-Chan Chen, Miaoli County, TW;

Chia-Jung Hsu, Hsinchu, TW;

Li-Yi Lin, Changhua County, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/394 (2020.01); G06F 119/06 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01);
Abstract

A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.


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