The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

Feb. 08, 2018
Applicant:

Université Du Luxembourg, Luxembourg, LU;

Inventors:

Marcus Völp, Luxembourg, LU;

Paulo Esteves-Veríssimo, Luxembourg, LU;

Jérémie Decouchant, Luxembourg, LU;

Vincent Rahli, Luxembourg, LU;

Francisco Rocha, Luxembourg, LU;

Assignee:

Université du Luxembourg, Luxembourg, LU;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/57 (2013.01); G06F 21/76 (2013.01);
U.S. Cl.
CPC ...
G06F 21/575 (2013.01); G06F 21/76 (2013.01); G06F 2221/034 (2013.01); G06F 2221/2141 (2013.01);
Abstract

There is disclosed a computing/data processing device comprising: a plurality of computing units, each computing unit comprising a computing resource; the computing device comprising at least three computing units, each computing unit comprising a/the same computing resource; each computing unit further comprising a computing unit access manager, each unit access manager being adapted to control access to the computing resource of the respective computing unit in response to at least one request; wherein, the computing unit access manager only allows a response to the at least one request if a majority of the computing units provide a same response to the at least one request; and wherein, the computing device comprising a network-on-a-chip, is provided on a chip and/or comprises an integrated chip (IC) or microprocessor. The IC beneficially comprises a Field-Programmable Gate Array (FPGA) device. In a preferred embodiment, the unit access manager controls access to the computing resource based on a token; the token comprising: a pointer to the respective computing resource, a set of rights relating to that computing resource, and a numerical representation of that computing resource.


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