The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2022
Filed:
Jul. 18, 2017
Applicant:
Cypress Semiconductor Corporation, San Jose, CA (US);
Inventors:
Jan-Willem Van de Waerdt, San Jose, CA (US);
Kai Dieffenbach, Egelsbach, DE;
Uwe Moslehner, Dreieich, DE;
Jens Wagner, Babenhausen, DE;
Mathias Sedner, Egelsbach, DE;
Venkat Natarajan, Sunnyvale, CA (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 5/00 (2006.01); G06F 12/14 (2006.01); G06F 13/42 (2006.01); G06F 21/57 (2013.01); G06F 21/76 (2013.01);
U.S. Cl.
CPC ...
G06F 12/1491 (2013.01); G06F 12/145 (2013.01); G06F 12/1441 (2013.01); G06F 12/1458 (2013.01); G06F 13/4282 (2013.01); G06F 21/572 (2013.01); G06F 21/76 (2013.01); G06F 2212/1052 (2013.01);
Abstract
A context-based protection system uses tiered protection structures including master protection units, shared memory protection units, a peripheral protection units to provide security to bus transfer operations between central processing units (CPUs), memory array or portions of arrays, and peripherals.