The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2022
Filed:
Mar. 29, 2019
Samsung Electronics Co., Ltd., Suwon-si, KR;
Sang-Wook Kim, Yongin-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
In a dissection method for layout patterns in a semiconductor device, a design layout is divided into a plurality of patches. A plurality of first dissection points for target layout patterns in the target patch and neighboring layout patterns in the neighboring patches are set based on vertexes of the target and neighboring layout patterns. At least one second dissection point for at least one exceptional layout pattern is set. The at least one exceptional layout pattern is a layout pattern in which the first dissection points are not set and which extends to pass through boundaries of one patch. A plurality of third dissection points for the target layout patterns and the neighboring layout patterns are set based on the first and second dissection points. The target layout patterns are divided into a plurality of target segments based on the first, second and third dissection points.