The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2022
Filed:
Nov. 06, 2017
Applicant:
Nissha Co., Ltd., Kyoto, JP;
Inventors:
Teppei Kimura, Kyoto, JP;
Hiroaki Suzuki, Kyoto, JP;
Assignee:
Nissha Co., Ltd., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 27/12 (2006.01); H01L 21/48 (2006.01); H01L 21/52 (2006.01); H01L 21/683 (2006.01); H01L 21/784 (2006.01); H01L 23/055 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G01N 27/12 (2013.01); H01L 21/4817 (2013.01); H01L 21/52 (2013.01); H01L 21/6836 (2013.01); H01L 21/784 (2013.01); H01L 23/055 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 24/97 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/95001 (2013.01);
Abstract
A package is configured such that a length in a direction parallel to a semiconductor chip is larger than a length in a direction orthogonal to the semiconductor chip, and the package includes a substrate to which the semiconductor chip is electrically connected and fixed, a side wall firmly attached to the substrate, and a cover firmly attached to the side wall. The package includes a detection space in which gas flows around the semiconductor chip. The package includes openings formed in the side wall and/or between the side wall and the cover and communicated with the detection space.