The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2022
Filed:
Feb. 24, 2021
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Sudhir Shrikantha Kudva, Dublin, CA (US);
Nikola Nedovic, San Jose, CA (US);
Carl Thomas Gray, Apex, NC (US);
Assignee:
NVIDIA Corp., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17768 (2020.01); H04L 9/32 (2006.01); H04L 9/08 (2006.01); H03K 19/173 (2006.01); H03K 19/17748 (2020.01); H03K 19/17704 (2020.01); H03K 19/17756 (2020.01); H03K 19/177 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17768 (2013.01); H03K 19/173 (2013.01); H03K 19/177 (2013.01); H03K 19/17708 (2013.01); H03K 19/17748 (2013.01); H03K 19/17756 (2013.01); H04L 9/0819 (2013.01); H04L 9/0861 (2013.01); H04L 9/3278 (2013.01);
Abstract
A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.