logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11411102 B1

PDFFull Text
Date of Patent:
Aug. 09, 2022

Filed:

Jan. 05, 2021

Semiconductor device

Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventor:

Atsushi Kurokawa, Nagaokakyo, JP;

Assignee:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Attorney:

Studebaker & Brackett PC

Primary Examiner:

Joseph C Nicely

Int. Cl.
CPC ...
H01L 29/737 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/3205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/737 (2013.01); H01L 21/3205 (2013.01); H01L 21/768 (2013.01); H01L 23/522 (2013.01); H01L 29/0817 (2013.01); H01L 29/0821 (2013.01); H01L 29/41708 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A semiconductor device includes an HBT; emitter wiring which is connected to an emitter electrode of the HBT and covers the HBT; a passivation film having an opening on the HBT in plan view; a UBM layer which is connected to the emitter wiring through the opening and made of a refractory metal with a thickness of 300 nm or more; and a pillar bump which is arranged on the UBM layer and includes a metal post and a solder layer. The UBM layer serves as a stress relaxation layer, thereby relaxing stress on the HBT due to a difference in thermal expansion coefficient between a GaAs-based material of each layer constituting the HBT and the pillar bump.

Find Patent Forward Citations

Kurokawa, Atsushi. (2022). Semiconductor device (U.S. Patent No. 11411102). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11411102

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…