Semiconductor device with fortifying layer

Abstract

Power transistors relying on planar MOS cell designs suffer from the 'hole drainage effect'; addition of an enhancement layer creates significant loss of breakdown voltage capability. The Fortified Enhanced Planar MOS cell design provides an alternative that uses enhancement layers, field oxides, and gate trenches without suffering from the loss of blocking voltage. A low doped P-type 'fortifying layer' reduces the high peak electric fields that develop in blocking mode in critical regions. The fortifying layer can be electrically biased through an additional electrical contact, which can be arranged at die level, not at transistor cell level. Due to the low dopant concentration of the fortifying layer, no additional MOS channels need to be formed, and the electrons will flow thru the non-inverted regions of the fortifying layer. The new design shows advantages in performance, ease of processing, and applicability.