The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Aug. 28, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Tomoya Sanuki, Yokkaichi Mie, JP;

Keisuke Nakatsuka, Kobe Hyogo, JP;

Hiroshi Maejima, Setagaya Tokyo, JP;

Kenichiro Yoshii, Bunkyo Tokyo, JP;

Takashi Maeda, Kamakura Kanagawa, JP;

Hideo Wada, Yokkaichi Mie, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11565 (2017.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 27/11578 (2017.01); H01L 27/11575 (2017.01); H01L 27/1157 (2017.01); H01L 27/11563 (2017.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11565 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/1157 (2013.01); H01L 27/11563 (2013.01); H01L 27/11568 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1424 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.


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