The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Feb. 16, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Thomas Kuenemund, Munich, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/40 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 2027/11861 (2013.01); H01L 2027/11875 (2013.01);
Abstract

A chip is described including a semiconductor layer including doped regions; a metallization layer on the semiconductor layer and at least one cell row including p-channel field effect transistors and n-channel field effect transistors, wherein the doped regions form source regions and drain regions of the p-channel field effect transistors and the n-channel field effect transistors; contacts extending from the source regions, the drain regions and gate regions of the p-channel field effect transistors and the n-channel field effect transistors to the metallization layer, wherein the metallization layer is structured in accordance with a metallization grid such that the p-channel field effect transistors and the n-channel field effect transistors are connected to form one or more logic gates.


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