The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Jun. 26, 2020
Applicant:

Ultramemory Inc., Tokyo, JP;

Inventors:

Ryuji Takishita, Tokyo, JP;

Takao Adachi, Tokyo, JP;

Assignee:

ULTRAMEMORY INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/04 (2014.01); H01L 25/07 (2006.01); H01L 25/11 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/3672 (2013.01); H01L 23/49811 (2013.01); H01L 24/45 (2013.01); H01L 25/042 (2013.01); H01L 25/0652 (2013.01); H01L 25/071 (2013.01); H01L 25/112 (2013.01); H01L 27/0203 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1435 (2013.01);
Abstract

The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor moduleis provided with: a logic chip; a pair of RAM unitseach composed of a lamination-type RAM module; a first interposerelectrically connected to the logic chip and to each of the pair of RAM units; and a connection unitthat communicatively connects the logic chip and each of the pair of RAM units, wherein one RAM unitis placed on the first interposer, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unittherebetween, and the other RAM unitis disposed so as to overlap the one RAM unitwith the connection unittherebetween, and is also disposed along the outer periphery of the logic chip.


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