The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Mar. 19, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyungeun Choi, Suwon-si, KR;

Eun-Ji Kim, Seoul, KR;

Jong-Ho Moon, Seoul, KR;

Hyoungyol Mun, Yongin-si, KR;

Han-Sik Yoo, Seongnam-si, KR;

Kiseok Lee, Hwaseong-si, KR;

Seungjae Jung, Suwon-si, KR;

Taehyun An, Seoul, KR;

Sangyeon Han, Suwon-si, KR;

Yoosang Hwang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); G11C 11/408 (2006.01); H01L 25/065 (2006.01); G11C 11/4091 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 27/10805 (2013.01); H01L 27/10897 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01);
Abstract

A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.


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