The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Dec. 19, 2020
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventor:

Bengt Littmann, Toronto, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 7/58 (2006.01); G06F 13/364 (2006.01); G06F 11/07 (2006.01); G06F 11/34 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4291 (2013.01); G06F 7/584 (2013.01); G06F 11/0706 (2013.01); G06F 11/0736 (2013.01); G06F 11/0751 (2013.01); G06F 11/3027 (2013.01); G06F 11/3485 (2013.01); G06F 13/364 (2013.01); G06F 13/4295 (2013.01); G06F 2213/0016 (2013.01);
Abstract

A shared bus for inter-channel communication comprising two or more channels having signal processing elements such that each channel is configured to receive and process an incoming channel specific signal. A sequence generator is configured to generate a test sequence suitable for testing the signal processing elements of a channel. An error checker is configured to error check incoming channel specific signals. A shared bus connects to the two or more channels to communicate an incoming channel specific signal to the error checker and communicate the test sequence to the signal processing elements of a channel. One or more pull up resistors and/or termination resistors connect to the shared bus. The bus may comprise a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The bus interface comprises an open collector current mode logic driver in cascode arrangement.


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