The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Sep. 18, 2020
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Cheng-Tien Wan, Hsinchu, TW;

Ming-Cheng Lee, Hsinchu, TW;

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 21/02532 (2013.01); H01L 21/02546 (2013.01); H01L 21/02549 (2013.01); H01L 21/02603 (2013.01); H01L 21/28255 (2013.01); H01L 21/28264 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/66522 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01);
Abstract

A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.


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