The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Jan. 16, 2020
Applicant:

Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Guangdong, CN;

Inventors:

Chuanbao Luo, Guangdong, CN;

Macai Lu, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78606 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/136209 (2013.01); G02F 1/136222 (2021.01); G02F 1/136227 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78633 (2013.01); H01L 27/3262 (2013.01); H01L 27/3272 (2013.01); H01L 27/3276 (2013.01);
Abstract

The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel. In the array substrate, a functional layer disposed between an active layer and a gate insulating layer protects the active layer during etching of the active layer, which prevents the active layer from damage and conducts a source/drain layer and the active layer, so that transistors in the array substrate work normally, solving the technical problem that current display panels damage the active layer during a preparation process, which causes performance of thin film transistors to decrease.


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