The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2022
Filed:
Feb. 12, 2021
Applicant:
Mqsemi Ag, Zug, CH;
Inventors:
Munaf Rahimo, Gaensbrunnen, CH;
Iulian Nistor, Niederweningen, CH;
Assignee:
mqSemi AG, Zug, CH;
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1095 (2013.01); H01L 29/0615 (2013.01); H01L 29/1608 (2013.01); H01L 29/407 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/42376 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01);
Abstract
A power transistor layout structure is described that includes a planar cell with a planar gate electrode forming an horizontal MOS channel, and a plurality of trench recesses with gate electrodes, which are arranged at various angles to the longitudinal direction of the planar cells. This cell concept can adopt both planar MOS channels, and Trench MOS channels in a single MOS cell structure. As an alternative, the planar cell gate electrode may be grounded. The device is easy to manufacture based on a self-aligned process with minimum number of masks, with the potential of applying additional layers.