The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Aug. 18, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Taejin Park, Gyeonggi-do, KR;

Chulkwon Park, Hwaseong-si, KR;

Soyeong Kim, Suwon-si, KR;

Eun A Kim, Seoul, KR;

Hyo-Sub Kim, Seoul, KR;

Sohyun Park, Seoul, KR;

Sunghee Han, Hwaseong-si, KR;

Yoosang Hwang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/41 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/76224 (2013.01); H01L 29/4011 (2019.08); H01L 29/41 (2013.01);
Abstract

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.


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