The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Dec. 02, 2020
Applicant:

Japan Display Inc., Tokyo, JP;

Inventor:

Satoshi Maruyama, Minato-ku, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/32 (2006.01); H01L 27/12 (2006.01); H01L 27/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3262 (2013.01); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 27/3265 (2013.01); H01L 27/3276 (2013.01); H01L 27/0688 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1262 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01); H01L 2227/323 (2013.01);
Abstract

A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.


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