The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Jun. 01, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kangyoon Choi, Seoul, KR;

Gilsung Lee, Seoul, KR;

Dong-Sik Lee, Hwaseong-si, KR;

Yongsik Yim, Seongnam-si, KR;

Eunsuk Cho, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 29/40117 (2019.08);
Abstract

Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.


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