The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Jun. 29, 2020
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Syuan-Rong Huang, Chiayi County, TW;

Chien-Huei Yang, Taoyuan, TW;

Chun-Fu Tung, Hsinchu, TW;

Hua-Ming Wang, Hsinchu County, TW;

Yung-Cheng Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/66 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); H01L 21/67288 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01);
Abstract

A system for determining the cause of an abnormality in a semiconductor manufacturing process includes an abnormality mode determination module, a selection module, and a root cause analysis module. The abnormality mode determination module is used to determine the similarity between wafer bin maps containing the abnormal data. When the similarity among the wafer maps is higher than a reference value, the selection module executes the steps of: determining a bad lot based on the wafer maps where the similarity is higher than the reference value; determining a time span within which the bad lot is generated; selecting other bad lots occurring in the time span and satisfying a failure model; selecting a good lot based on a fixed lot interval. The root cause analysis module is used to execute the steps of calculating the correlation among data to obtain confidence indexes.


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