The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Feb. 11, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Ravi Kumar, Redwood City, CA (US);

Deepanshu Dutta, Fremont, CA (US);

Vishwanath Basavaegowda Shanthakumar, Milpitas, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/26 (2006.01); G06F 11/10 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G06F 11/1068 (2013.01); G11C 16/3459 (2013.01); G11C 16/0483 (2013.01);
Abstract

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to a word line and arranged in one of a plurality of blocks and configured to retain a threshold voltage corresponding to a data state. The memory cells are operable in one of a first read condition in which a word line voltage is discharged and a second read condition in which the word line voltage is coupled up to a residual voltage level. A control circuit determines a power on event and periodically apply a predetermined refresh read voltage to the word line for a predetermined period of time for each of the plurality of blocks at a specified interval based on at least one data retention factor to maintain the memory cells of the plurality of blocks in the second read condition in response to determining the power on event.


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