The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Aug. 13, 2020
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Chang Kyun Park, Gyeonggi-do, KR;

Young Sik Koh, Gyeonggi-do, KR;

Seung Jin Park, Gyeonggi-do, KR;

Dong Hyun Lee, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 8/18 (2006.01); G11C 7/22 (2006.01); G11C 16/32 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/1072 (2013.01); G11C 7/222 (2013.01); G11C 11/4076 (2013.01); G11C 16/32 (2013.01); G11C 2207/2272 (2013.01);
Abstract

A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.


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