The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Oct. 13, 2020
Applicant:

Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

Fangong Gong, Beijing, CN;

Mengchen Yang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3802 (2013.01); G06F 9/30047 (2013.01); G06F 9/321 (2013.01); G06F 9/3806 (2013.01); G06F 9/3808 (2013.01); G06F 9/3822 (2013.01); G06F 9/3861 (2013.01); G06F 9/3885 (2013.01); G06F 12/0875 (2013.01); G06F 9/3848 (2013.01); G06F 2212/452 (2013.01);
Abstract

A microprocessor is shown, in which a branch predictor and an instruction cache are decoupled by a fetch-target queue (FTQ). The branch predictor performs branch prediction for N instruction addresses in parallel in the same cycle, wherein N is an integer greater than 1. In the current cycle, the branch predictor finishes branch prediction for N instruction addresses in parallel and, among the N instruction addresses with finished branch prediction, those that are not bypassed and do not overlap previously-predicted instruction addresses are pushed into the fetch-target queue, to be read out later as an instruction-fetching address for the instruction cache. The previously-predicted instruction addresses are pushed into the fetch-target queue in a previous cycle.


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