The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2022
Filed:
Aug. 06, 2021
Applicant:
Cisco Technology, Inc., San Jose, CA (US);
Inventors:
Abhishek Bhat, Breinigsville, PA (US);
Romesh Kumar Nandwana, Breinigsville, PA (US);
Assignee:
Cisco Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/107 (2006.01); H03L 7/099 (2006.01); H03L 7/091 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1075 (2013.01); H03L 7/091 (2013.01); H03L 7/099 (2013.01);
Abstract
A clock generator includes a first phase-locked loop (PLL), a converter circuit, and a second PLL. The first PLL generates an oscillating signal based on a reference signal and outputs a noise signal indicating a noise component of the oscillating signal. The converter circuit produces an electrical signal based on the noise signal. The second PLL receives the electrical signal from the converter circuit at a loop filter of the second PLL and generates a clock signal based on the oscillating signal and the electrical signal.