The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2022

Filed:

Feb. 26, 2021
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Ryoichi Kato, Kawasaki, JP;

Yuma Murata, Kawasaki, JP;

Naoyuki Kanai, Kawasaki, JP;

Akito Nakagome, Kawasaki, JP;

Yoshinari Ikeda, Kawasaki, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H05K 1/02 (2006.01); H05K 1/14 (2006.01);
U.S. Cl.
CPC ...
H01L 24/48 (2013.01); H01L 23/49844 (2013.01); H01L 24/32 (2013.01); H01L 24/40 (2013.01); H01L 25/072 (2013.01); H05K 1/0298 (2013.01); H05K 1/142 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/40137 (2013.01); H01L 2224/48175 (2013.01);
Abstract

A semiconductor module includes an insulating substrate having a main wiring layer, positive and negative electrode terminals adjacently arranged in a first direction, a plurality of semiconductor elements forming a first column and another plurality of semiconductor elements forming a second column, each semiconductor element having gate and source electrode on an upper surface thereof, and being disposed on the main wiring layer such that corresponding ones of the gate electrodes in the first and second columns face each other in a second direction orthogonal to the first direction, a control wiring substrate between the first and second columns and having gate and source wiring layers, a gate wiring member connecting ones of the gate electrodes in the first and second columns through the gate wiring layer, and a source wiring member connecting ones of the source electrodes in the first and second columns through the source wiring layer.


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