The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2022

Filed:

Feb. 24, 2020
Applicant:

Ngk Insulators, Ltd., Nagoya, JP;

Inventors:

Yuji Akatsuka, Handa, JP;

Masaki Ishikawa, Handa, JP;

Kazuhiro Nobori, Handa, JP;

Akiyoshi Hattori, Nagoya, JP;

Keiichi Nakamura, Handa, JP;

Assignee:

NGK Insulators, Ltd., Nagoya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/687 (2006.01); C04B 35/515 (2006.01); H01J 37/32 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 21/68757 (2013.01); C04B 35/515 (2013.01); H01J 37/32715 (2013.01); H01L 21/6833 (2013.01); H01L 21/68785 (2013.01);
Abstract

A wafer mounting table includes a first electrode and a second electrode buried inside of a ceramic substrate having a wafer mounting surface so as to be parallel to the wafer mounting surface with the first electrode closer to the wafer mounting surface than the second electrode. The wafer mounting table includes a conductive section that electrically conducts the first electrode and the second electrode. The conductive section is such that a plurality of circular members comprised of plate-shaped metal meshes parallel to the wafer mounting surface are stacked between the first electrode and the second electrode.


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