The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

May. 14, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Steven L. Pope, Cambridge, GB;

Derek Roberts, Cambridge, GB;

David J. Riddoch, Huntingdon, GB;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 67/10 (2022.01); H04L 45/00 (2022.01); H04L 9/40 (2022.01); G06F 9/50 (2006.01); H04L 49/00 (2022.01); H04L 67/59 (2022.01); H04L 43/00 (2022.01); G06N 20/00 (2019.01); G06F 16/21 (2019.01); H04L 69/16 (2022.01);
U.S. Cl.
CPC ...
H04L 67/10 (2013.01); G06F 9/5044 (2013.01); H04L 45/38 (2013.01); H04L 49/30 (2013.01); H04L 63/1416 (2013.01); H04L 63/1458 (2013.01); H04L 63/166 (2013.01); H04L 67/2861 (2013.01); G06F 16/213 (2019.01); G06F 2209/509 (2013.01); G06N 20/00 (2019.01); H04L 43/14 (2013.01); H04L 69/16 (2013.01);
Abstract

A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.


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