The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Sep. 23, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Abhirup Lahiri, Dublin, IE;

Roberto Pelliconi, Imola, IT;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H04B 1/00 (2006.01); H03M 1/36 (2006.01); H02M 3/156 (2006.01);
U.S. Cl.
CPC ...
H03M 1/661 (2013.01); H02M 3/156 (2013.01); H03M 1/362 (2013.01); H04B 1/0007 (2013.01);
Abstract

A DAC cell includes first and second transistors, drain-source coupled at a first node, a gate of the second transistor coupled to a data input (D), and third and fourth transistors, drain-source coupled at a second node, a gate of the fourth transistor coupled to a complement of the data input (DB). The circuit further includes first and second shadow transistors each coupled between the first node and ground, a gate of the first shadow transistor coupled to a switching input (S) and a gate of the second shadow transistor coupled to a complement of the switching input (SB). The circuit still further includes third and fourth shadow transistors each coupled between the second node and ground, a gate of the third shadow transistor coupled to S and a gate of the fourth shadow transistor coupled to SB.


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