The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Feb. 10, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Shibun Tsuda, Tokyo, JP;

Tomohiro Yamashita, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 29/792 (2006.01); H01L 27/11573 (2017.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/11573 (2013.01); H01L 29/0653 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/66833 (2013.01); H01L 29/7851 (2013.01); H01L 29/792 (2013.01); H01L 29/7923 (2013.01);
Abstract

When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.


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