The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Nov. 19, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Eisuke Takii, Yokkaichi, JP;

Hiraku Hashimoto, Yokkaichi, JP;

Shin Koyama, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 27/11573 (2017.01); H01L 23/528 (2006.01); H01L 27/11556 (2017.01); H01L 27/11529 (2017.01); H01L 27/11582 (2017.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract

A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures, source-level material layers, and a three-dimensional memory array including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film. A vertically alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. A through-memory-level interconnection via structure vertically extends through each plate within the vertically alternating sequence and contacts a center portion of a top surface of one of the lower-level metal interconnect structures. At least one silicon nitride liner prevents or reduces oxidation of the lower-level metal interconnect structures underneath the through-memory-level interconnection via structure.


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