The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Jul. 07, 2020
Applicant:

King Abdullah University of Science and Technology, Thuwal, SA;

Inventors:

Rawan Naous, Thuwal, SA;

Khaled Nabil Salama, Thuwal, SA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); H03K 19/21 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0021 (2013.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01); G11C 2213/15 (2013.01);
Abstract

In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.


Find Patent Forward Citations

Naous, Rawan. (2022). Stochastic memristor logic devices (U.S. Patent No. 11393527). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11393527

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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