The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Dec. 20, 2021
Applicant:

Quadric.io, Inc., Burlingame, CA (US);

Inventors:

Aman Sikka, Burlingame, CA (US);

Nigel Drego, Burlingame, CA (US);

Daniel Firu, Burlingame, CA (US);

Veerbhan Kheterpal, Burlingame, CA (US);

Assignee:

quadric.io, Inc., Burlingame, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/14 (2006.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 17/142 (2013.01); G06F 17/16 (2013.01);
Abstract

Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.


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