The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Feb. 01, 2019
Applicant:

Liqid Inc., Broomfield, CO (US);

Inventors:

James Scott Cannata, Denver, CO (US);

Christopher R. Long, Colorado Springs, CO (US);

Phillip Clark, Boulder, CO (US);

Sumit Puri, Calabasas, CA (US);

Assignee:

Liqid Inc., Broomfield, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 13/40 (2006.01); G06F 13/20 (2006.01); G06F 13/42 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 9/4411 (2013.01); G06F 13/20 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes instructing a PCIe fabric communicatively coupling a plurality of physical computing components including PCIe devices and one or more PCIe switches to establish a first PCIe communication path between the management processor and a target PCIe device. The method also includes directing at least configuration data to the target PCIe device using the first PCIe communication path and instructing the PCIe fabric to remove the first PCIe communication path between the management processor and the target PCIe device. The method also includes instructing the PCIe fabric to establish a second PCIe communication path between a selected PCIe device and the target PCIe device configured according to the configuration data.


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