The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Jul. 24, 2020
Applicant:

AU Optronics Corporation, Hsinchu, TW;

Inventors:

Cheng-Chan Wang, Hsinchu, TW;

Tsai-Sheng Lo, Hsinchu, TW;

Chia-Hsin Chung, Hsinchu, TW;

Chih-Chiang Chen, Hsinchu, TW;

Hui-Ku Chang, Hsinchu, TW;

Sheng-Kai Lin, Hsinchu, TW;

Chia-Po Lin, Hsinchu, TW;

Ming-Jui Wang, Hsinchu, TW;

Sheng-Ming Huang, Hsinchu, TW;

Jen-Kuei Lu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1333 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/136227 (2013.01); H01L 27/124 (2013.01); H01L 27/1288 (2013.01); H01L 29/78633 (2013.01); G02F 1/136218 (2021.01); G02F 1/136295 (2021.01);
Abstract

An active device substrate including a substrate, first metal grid wires, a first transparent conductive layer, a gate insulating layer, a semiconductor layer, a source, and a drain is provided. The first metal grid wires are located on the substrate. The first transparent conductive layer includes a scan line and a gate connected to the scan line. The scan line and/or the gate is directly connected to at least a part of the first metal grid wires. The gate insulating layer is located on the first transparent conductive layer. The semiconductor layer is located on the gate insulating layer and overlapped with the gate. The source and the drain are electrically connected to the semiconductor layer.


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