The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Mar. 04, 2019
Applicant:

Analog Devices International Unlimited Company, County Limerick, IE;

Inventors:

Javier A. Salcedo, North Billerica, MA (US);

Srivatsan Parthasarathy, Acton, MA (US);

Enrique C. Bosch, Alginet, ES;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H01L 27/02 (2006.01); H01L 29/739 (2006.01); H01L 29/08 (2006.01); H02H 11/00 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H01L 27/0255 (2013.01); H01L 27/0262 (2013.01); H01L 29/0834 (2013.01); H01L 29/0839 (2013.01); H01L 29/7391 (2013.01); H02H 11/002 (2013.01);
Abstract

High voltage tolerant electrical overstress protection with low leakage current and low capacitance is provided. In one embodiment, a semiconductor die includes a signal pad, an internal circuit electrically connected to the signal pad, a power clamp electrically connected to an isolated node, and one or more isolation blocking voltage devices electrically connected between the signal pad and the isolated node. The one or more isolation blocking voltage devices are operable to isolate the signal pad from a capacitance of the power clamp. In another embodiment, a semiconductor die includes a signal pad, a ground pad, a high voltage/high speed internal circuit electrically connected to the signal pad, and a first thyristor and a second thyristor between the signal pad and the ground pad.


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