The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Jan. 22, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Qintao Zhang, Mt. Kisco, NY (US);

Samphy Hong, Saratoga Springs, NY (US);

Lei Zhong, Austin, TX (US);

David Jon Lee, Poughkeepsie, NY (US);

Felix Levitov, Ballston Lake, NY (US);

Carlos Caballero, Covina, CA (US);

Durgaprasad Chaturvedula, San Jose, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42368 (2013.01); H01L 29/6656 (2013.01); H01L 29/66068 (2013.01); H01L 29/78 (2013.01);
Abstract

A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.


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