The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Sep. 10, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Mutsumi Okajima, Yokkaichi Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 25/18 (2006.01); H01L 27/22 (2006.01); H01L 27/108 (2006.01); H01L 23/00 (2006.01); H01L 21/02 (2006.01); G11C 11/407 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); G11C 11/161 (2013.01); G11C 11/407 (2013.01); H01L 21/02244 (2013.01); H01L 21/02258 (2013.01); H01L 27/10852 (2013.01); H01L 27/224 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/8013 (2013.01); H01L 2924/1436 (2013.01);
Abstract

According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.


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