The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Jun. 19, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jin Ho Kim, Icheon-si, KR;

Young Ki Kim, Icheon-si, KR;

Sang Hyun Sung, Icheon-si, KR;

Sung Lae Oh, Icheon-si, KR;

Byung Hyun Jun, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/552 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 28/60 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06537 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19104 (2013.01); H01L 2924/3025 (2013.01);
Abstract

A semiconductor memory device includes a plurality of first pads disposed in one surface of a memory chip which includes a memory cell array and a plurality of row lines coupled to the memory cell array, and coupled to the row lines, respectively; and a plurality of second pads disposed in one surface of a circuit chip which is boned to the one surface of the memory chip, coupled to pass transistors, respectively, of the circuit chip, and bonded to the first pads, respectively. The second pads are aligned with the pass transistors, with the same pitch as a pitch of the pass transistors.


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