The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11387166 B1

Date of Patent:

Jul. 12, 2022

Filed:

Nov. 27, 2019

Three-dimensional memory device with variable width contact via structures and methods for making the same

Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventor:

Keigo Kitazawa, Nagoya, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group PLLC

Primary Examiner:

Grant S Withers

Int. Cl.

CPC ...

H01L 27/11565 (2017.01); H01L 23/48 (2006.01); H01L 27/1157 (2017.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 27/11519 (2017.01); H01L 27/11548 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01);

U.S. Cl.

CPC ...

H01L 23/481 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01);

Abstract

Devices are formed on a substrate. A first-tier alternating stack of first insulating layers and first spacer material layers having first stepped surfaces and a first retro-stepped dielectric material portion are formed over the substrate. A sacrificial contact via structure is formed through the first retro-stepped dielectric material portion. A second-tier alternating stack of second insulating layers and second spacer material layers is formed with second stepped surfaces. A second retro-stepped dielectric material portion including a doped silicate glass liner and a silicate glass material portion is formed over the second stepped surfaces. Memory stack structures are formed through the second-tier alternating stack and the first-tier alternating stack. A contact via cavity is formed down to the sacrificial contact via structure. The doped silicate glass liner is recessed and the sacrificial contact via structure is removed, to form a contact via structure in the contact via cavity.

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