The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Sep. 27, 2021
Applicant:

China Flash Co., Ltd., Shanghai, CN;

Inventors:

Hong Nie, Shanghai, CN;

Jingwei Chen, Shanghai, CN;

Assignee:

CHINA FLASH CO., LTD., Shanghai, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/12 (2006.01);
U.S. Cl.
CPC ...
G11C 16/102 (2013.01); G11C 16/12 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01);
Abstract

The present disclosure relates to a method for programming a 3D NAND flash memory, which includes: S) providing a 3D flash memory array, and eliminating residual charges; S) strobing a bit line where an upper sub-storage module is located; S) applying a drain voltage to the drain of a to-be-programmed memory cell, and floating a source thereof; S) applying a programming voltage to the gate of the to-be-programmed memory cell, to complete programming; and S) after completing the programming of the upper sub-storage module, and when the upper sub-storage module keeps a programmed state, strobing a bit line where a lower sub-storage module is located, and repeating operation S) and operation S) to achieve programming of the lower sub-storage module. In the method for programming a 3D NAND flash memory according to the present disclosure, programming is completed based on tertiary electron collision.


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