The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Nov. 24, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Norichika Asaoka, Yokohama Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/04 (2006.01); G11C 16/32 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01);
Abstract

A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.


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